For a semiconductor die, the circuit components within the integrated circuit core are connected with outer components through bond pads disposed on the surface of the die. In general, several hundreds of bond pads are distributed on the periphery of a die. There are two kinds of bond pad design, one is linear arrangement, the other is staggered arrangement. The linear bond pad arrangement is shown in FIG. 1. Only one bank of bond pads are disposed in one side of a die. For a linear arrangement, only finite number of bond pads are disposed in a die since if too many bond pads are arranged, the die area must be increased dramatically so that the cost of die is also increased largely. Another arrangement is staggered bond pad arrangement, wherein, each side has two banks of bond pads which are staggered, as shown in FIG. 2. The staggered bond pad arrangement has the advantage of compactness.
The staggered bond pads can be divided into a plurality of basic bond pad units having a shape of three staggered rectangles as that shown in FIG. 3, which is formed by three bond pads arranged as three staggered rectangles. In the basic unit, bond pads are spaced by a trace (classically, formed by the alloy of aluminum and copper) and a layer of dielectric material is filled between the bond pad and the trace as an insulator.
With reference to FIG. 4, in general, there are many layers of bond pads. Only the first layer is located on the surface of the die, which the other layer is embedded into the die. The bond pads of different layers are communicated through at least one via hole, while the whole bond pad layers are connected with the circuit component in the integrated circuit core through at least one contact hole. Then the surface of the die is enclosed by a passivation layer, only the bond pad opening of each bond pad is exposed outwards for communicating with other wires.
In the design of an integrated circuit, it is desired that the die area is small, since the smaller the die area, the greater the unit product amount in a chip unit, and accordingly the cost is reduced, However, the size of a die is mainly determined by the size of banks of bond pads. That is to say if we can reduce the size of the three staggered rectangle unit, then the size of the die is also reduced. For example, with reference to FIG. 3. if originally, in the basic bond pad unit, the size of a bond pad is X mils, while the distance of the different banks are 126um. I we can reduce further this distance by 10% both in longitudinal and transversal directions, then the whole size of the die is reduced by 10%, namely, 0.9 times of the original size, and the area is reduced to 0.81 times of the original area. That is, with the chip of the same size, the amount of product becomes 125% with an increment of 25%. Therefore, all the manufacturers of integrated circuits make a great effort to reduce the size of the die, since this may create large profit.